parallel architecture
英 [ˈpærəlel ˈɑːkɪtektʃə(r)]
美 [ˈpærəlel ˈɑːrkɪtektʃər]
网络 平行架构; 并行系统结构; 平行构架; 平行架構; 平行结构
双语例句
- The system consists of two subsystems being in double CPU parallel architecture.
该系统由双CPU并行式结构的两个子系统构成。 - A logging data processing system based on fast distributed and parallel architecture
基于高速分布式并行结构的测井数据处理系统 - Compared with the full parallel architecture, the memory cost of the designed processor decreases, thus the speed is higher than that of the SDF pipeline architecture.
该处理器内存资源消耗较并行结构有所减少，运算速度较单独的SDF流水线结构有所提高。 - Microprocessor Design for Fine Granularity Explicit Parallel Architecture
细粒度显式并行体系结构微处理器设计 - The scheme of complex demodulation, using parallel architecture, was provided.
采用并联式复解调方案利用开关电流技术实现连续小波变换。 - A parallel architecture of m sequence pseudorandom code generator is presented, which can lower the power dissipation significantly.
提出了一种可以显著降低伪随机码发生器功耗的m序列伪随机码发生器并行实现结构。 - A two-phase parallel architecture is also proposed, which can achieve the possible maximum speed.
在不增加电路代价的前提下，获得了两倍于传统主－从型结构的速度。在此基础上，提出双相并行结构，从理论上分析，可得到最高的移位速度。 - Based on the character of the three step search algorithm ( 3SS), the architecture for motion estimation is studied. A parallel architecture for 3SS is presented, in which the repetitive data are reused.
根据三步搜索法的特点，研究了运动估计的实现结构，提出了一种基于并行结构的三步搜索算法实现方法。 - Cmrc& research on robot controller with multi DSP parallel architecture
CMRC&多DSP并行结构机器人控制器的研究 - BSP model is independent of parallel architecture. It is a parallel computing model, as well as a parallel program design model.
BSP模型独立于并行体系结构，既可作为并行计算模型，又可作为并行程序设计模型。 - VLSI Implementation for Video Processing IP Module Based on Synchronous and Parallel Architecture
基于同步并行结构的视频处理IP模块的VLSI设计 - For fully utilizing the powerful calculation capacity of GPU, we develop a parallel architecture for codec based on GPU+ CPU system. We also advance a series of video coding algorithms that are fit for GPU.
为了充分发挥GPU的计算能力，本文提出了CPU+GPU的并行编解码器架构，并在此基础上，设计了一系列适合于GPU实现的编解码算法。 - The paper studies the parallel manipulator force control algorithm based on computer parallel architecture, designs a system for dual-computer system parallel processing, The method quickens the parallel manipulator control algorithm processing, realizes the real-time force control and improves the manipulator control performance.
对并联机器人力控制算法基于并行结构的计算进行了研究，设计了并行处理双机系统结构。采用文中的处理方法大大提高了并联机器人力控制算法的处理速度，保证了实时力控制。 - At last, it describes the scalable parallel architecture of advanced WP system based on multiple SHARCs.
最后分析了基于多SHARC的VVP可扩展并行处理系统的组成方式和结构特点。 - The main object of this dissertation focuses on high-speed video decoder, one of the key components of HDTV. The methodology of design, parallel architecture, control strategy, simulation and optimizing of high-speed video decoder are studied.
本文以高清晰度数字电视的核心部件之一&高速视频解码器为研究对象，从设计方法学、并行结构、控制策略和仿真优化等方面对高速视频解码器的设计进行了深入研究。 - For the needs of practical application, this paper designed a necessary parallel architecture of realizing elliptic curve cryptosystem and designed the parallel algorithm.
为了实际应用的需要，本文设计了实现椭圆曲线密码体制所需的并行环境，并建立了并行算法。 - Research on a Parallel Architecture for Data Mining
一种面向数据挖掘的并行体系结构研究 - This paper introduces a fully digital broadband receiver with an FFT parallel architecture. The receiver is composed of three main functional parts: carrier recovery, timed recovery and matching filter.
介绍了一种FFT并行结构的全数字宽带接收机，接收机中包括载波恢复、定时恢复和匹配滤波器三个主要功能部分。 - Column group allocation project, as a kind of blocks allocation projects in MPI system with loop blocking, is provided in this paper, and also the algorithm to caculate the allocated block size in different parallel architecture.
提出了循环分块在MPI系统中的块分配方案&列组分配方案，并给出了在不同并行体系结构下依据列组分配方案计算块分配大小的算法。 - This paper studies the parallel architecture of high-speed video decoder by the force of parallel processing technic.
本文着重从并行处理技术为切入点对高速视频解码器并行结构的设计方法进行了深入的研究。 - The thesis analyses the key technology of computer parallel architecture by constructing a system for dual-computer system parallel processing.
本文通过构建一个并行处理双机系统分析了计算机并行系统的关键技术。 - The chapter expounds our hierarchical parallel architecture of decoder, original multiple channel algorithms and a load-balancing algorithm between GPU and CPU.
具体阐述了本文所提出的分级的并行解码器架构，独创的反量化、IDCT和运动补偿的多通道算法，以及GPU和CPU之间的负载均衡算法。 - With W-scan and parallel architecture, the transform speed and the efficiency is increased.
采用W扫描输入方式和行列并行处理结构，加快了变换速度，大大提高了小波变换的效率。 - On the basis of the parallel architecture and hardware characteristic of GPU, the parallel algorithm introduces three speedup methods to improve the implementation performance: execution configuration technology, high-speed storage technology and global storage technology optimizes the data storage structure and improves the data access efficiency.
并行算法系根据GPU的并行结构和硬件特点，采用执行配置技术、高速存储技术和全局存储技术三种加速技术，优化了数据存储结构，提高了数据访问效率。 - Especially, parallel architecture of ASIP can achieve a design with high parallelism and complexity.
尤其是ASIP的并行结构能够实现并行性和复杂度很高的设计。 - Architecture of the streaming spatial data server system is proposed based on the analysis of massive storage system and distributed parallel architecture.
在分析海量存储系统及分布式并行体系结构的基础上，设计了一种支持海量空间流媒体管理与服务的空间流媒体服务器的分布式并行体系结构。 - The proposed parallel ECC point addition and doubling scheduling algorithms are mapped on a parallel architecture that is based on VLIW processor techniques.
在协处理器中，提出了一种基于超长指令字（VLIW）的并行处理架构对ECC并行调度算法进行映射。 - So in this paper, parallel architecture of Eye-controlled mouse embedded system was proposed to provide customers with high-speed position calculation. Sequentially, the system can be divided into three phases, background processing, base location of initialization and real time controlling.
本文针对这一问题设计嵌入式眼控鼠标系统的并行架构，为客户提供高速定位计算。眼控鼠标系统在时序上分为背景处理，基准位置初始化和实时控制三个阶段。 - Based on the full use of parallel architecture, an efficient solution for VLSI implementation is described.
在采用并行结构的基础上，给出了一种高效的VLSI实现方案。 - The eye-mouse system version PC requires a lot of system resources, cause the PC can not handle other work well. If using multi-core parallel architecture, embedded eye-mouse system can achieve real-time control the mouse system.
PC版的眼标系统需要耗费大量的系统资源，影响PC处理其他的工作，嵌入式的眼标系统如果采用多核并行架构，则可以实现眼标系统的实时控制。